2449 search results - page 170 / 490 » VLSI |
132
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DFT
1994
IEEE
15 years 8 months ago
1994
IEEE
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
128
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VLSID
1994
IEEE
15 years 8 months ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
107
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VLSID
1994
IEEE
15 years 8 months ago
1994
IEEE
In this paper, we propose an architecture synthesis methodolog `to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate A m y s (FP...
167
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DFT
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
100
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VLSID
2010
IEEE
15 years 8 months ago
2010
IEEE
—We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET. The model is based on the EKV formalism and is valid in all r...