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VLSID
2004
IEEE
142views VLSI» more  VLSID 2004»
16 years 4 months ago
Dynamic Noise Margin: Definitions and Model
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
Li Ding 0002, Pinaki Mazumder
VLSID
2004
IEEE
111views VLSI» more  VLSID 2004»
16 years 4 months ago
On Buffering Schemes for Long Multi-Layer Nets
We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution...
Vani Prasad, Madhav P. Desai
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
16 years 4 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
ICCD
2001
IEEE
176views Hardware» more  ICCD 2001»
16 years 1 months ago
BDD Variable Ordering by Scatter Search
Reduced Ordered Binary Decision Diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI Design Automation. ...
William N. N. Hung, Xiaoyu Song
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
16 years 1 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim