Sciweavers

2449 search results - page 182 / 490
» VLSI
Sort
View
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
15 years 10 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
15 years 10 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
ISVLSI
2008
IEEE
161views VLSI» more  ISVLSI 2008»
15 years 10 months ago
Impact of Technology Scaling on Digital Subthreshold Circuits
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
15 years 10 months ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
ISVLSI
2008
IEEE
126views VLSI» more  ISVLSI 2008»
15 years 10 months ago
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Run...