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VLSI
2007
Springer
15 years 10 months ago
Use of gray decoding for implementation of symmetric functions
— This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity ReedMuller (F...
Osnat Keren, Ilya Levin, Radomir S. Stankovic
APCCAS
2006
IEEE
292views Hardware» more  APCCAS 2006»
15 years 10 months ago
Another Look at the Sequential Multiplier over Normal Bases
—The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m ), which can perform multiplication in m clock cycles for the normal basis. In this ar...
Zih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Y...
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
15 years 10 months ago
A simulation methodology for reliability analysis in multi-core SoCs
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf...
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra