2449 search results - page 188 / 490 » VLSI |
100
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
150
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
138
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
110
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
124
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...