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GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
15 years 10 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
15 years 10 months ago
Increasing design space of the instruction queue with tag coding
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
Junwei Zhou, Andrew Mason
ICRA
2005
IEEE
155views Robotics» more  ICRA 2005»
15 years 10 months ago
CPG Design using Inhibitory Networks
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
M. Anthony Lewis, Francesco Tenore, Ralph Etienne-...
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ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 10 months ago
Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
Valentin Gies, Thierry M. Bernard, Alain Mé...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 10 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton