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ASPDAC
2005
ACM
65views Hardware» more  ASPDAC 2005»
15 years 9 months ago
Library cell layout with Alt-PSM compliance and composability
The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET)....
Ke Cao, Puneet Dhawan, Jiang Hu
SBCCI
2005
ACM
136views VLSI» more  SBCCI 2005»
15 years 9 months ago
Current mask generation: a transistor level security against DPA attacks
The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or elect...
Daniel Mesquita, Jean-Denis Techer, Lionel Torres,...
VLSI
2005
Springer
15 years 9 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
15 years 9 months ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
15 years 9 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
Magdy A. El-Moursy, Eby G. Friedman