2449 search results - page 192 / 490 » VLSI |
119
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DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
162
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DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
122
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DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
138
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FCCM
2002
IEEE
15 years 9 months ago
2002
IEEE
This paper presents an FPGA-based design and implementation of a three dimensional (3D) triangle mesh decompressor. Triangle mesh is the dominant representation of 3D geometric mo...
138
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FCCM
2002
IEEE
15 years 9 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...