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HOTI
2002
IEEE
15 years 9 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
129
Voted
ISVLSI
2002
IEEE
81views VLSI» more  ISVLSI 2002»
15 years 9 months ago
Impact of Technology Scaling in the Clock System Power
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
ISVLSI
2002
IEEE
93views VLSI» more  ISVLSI 2002»
15 years 9 months ago
Temperature Variable Supply Voltage for Power Reduction
The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipatio...
Kaveh Shakeri, James D. Meindl
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
15 years 9 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...