2449 search results - page 197 / 490 » VLSI |
147
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GLVLSI
2000
IEEE
15 years 8 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
160
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GLVLSI
2000
IEEE
15 years 8 months ago
2000
IEEE
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...
129
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VLSID
2000
IEEE
15 years 8 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
131
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VLSID
2000
IEEE
15 years 8 months ago
2000
IEEE
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
133
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VLSID
2000
IEEE
15 years 8 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...