2449 search results - page 204 / 490 » VLSI |
111
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VLSID
1997
IEEE
15 years 8 months ago
1997
IEEE
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
180
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GLVLSI
1996
IEEE
15 years 8 months ago
1996
IEEE
Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...
132
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EURODAC
1994
IEEE
15 years 8 months ago
1994
IEEE
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
121
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ICCD
1993
IEEE
15 years 8 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
116
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VLSID
1993
IEEE
15 years 8 months ago
1993
IEEE
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...