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FCCM
2009
IEEE
204views VLSI» more  FCCM 2009»
15 years 8 months ago
Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
Geometric algebra (GA) is a mathematical framework that allows the compact description of geometric relationships and algorithms in many fields of science and engineering. The exe...
Holger Lange, Florian Stock, Andreas Koch, Dietmar...
DFT
2004
IEEE
174views VLSI» more  DFT 2004»
15 years 8 months ago
Defect Avoidance in a 3-D Heterogeneous Sensor
A 3D Heterogeneous Sensor using a stacked chip is investigated. Optical Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned col...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 8 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
15 years 8 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
DFT
2004
IEEE
94views VLSI» more  DFT 2004»
15 years 8 months ago
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n1, m, 3) convolutional...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...