Sciweavers

2449 search results - page 210 / 490
» VLSI
Sort
View
ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
15 years 8 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
ARVLSI
1995
IEEE
179views VLSI» more  ARVLSI 1995»
15 years 8 months ago
Algorithms for the optimal state assignment of asynchronous state machines
This paper presents a method for the optimal state assignment of asynchronous state machines. Unlike state assignment for synchronous state machines, state codes must be chosen ca...
Robert M. Fuhrer, Bill Lin, Steven M. Nowick
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
15 years 8 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
15 years 8 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
PARLE
1987
15 years 8 months ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch