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GLVLSI
2007
IEEE
186views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Block placement to ensure channel routability
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghav...
GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
15 years 4 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
ALGORITHMICA
2002
116views more  ALGORITHMICA 2002»
15 years 4 months ago
Budget Management with Applications
Given a directed acyclic graph with timing constraints, the budget management problem is to assigntoeachvertexanincrementaldelaysuchthatthesumofthesedelaysismaximizedwithoutviolati...
Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastav...
VLSI
2010
Springer
15 years 2 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...