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VLSID
2005
IEEE
153views VLSI» more  VLSID 2005»
16 years 4 months ago
Electromigration-Aware Physical Design of Integrated Circuits
The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC desi...
Göran Jerke, Jens Lienig
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
16 years 4 months ago
High-Performance Power Grids For Nanometer Technologies
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
Sachin S. Sapatnekar
131
Voted
VLSID
2002
IEEE
75views VLSI» more  VLSID 2002»
16 years 4 months ago
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, M...
FCCM
2008
IEEE
99views VLSI» more  FCCM 2008»
15 years 11 months ago
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit col...
Saar Drimer, Tim Güneysu, Christof Paar
ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...