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GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
15 years 11 months ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
15 years 11 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 11 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
15 years 11 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
15 years 11 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...