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GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
15 years 11 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
15 years 11 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 11 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
GLVLSI
2005
IEEE
110views VLSI» more  GLVLSI 2005»
15 years 11 months ago
QCA channel routing with wire crossing minimization
Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemica...
Brian Stephen Smith, Sung Kyu Lim
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
15 years 11 months ago
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
Vishal Suthar, Shantanu Dutt