Sciweavers

2449 search results - page 236 / 490
» VLSI
Sort
View
136
Voted
ASYNC
2003
IEEE
73views Hardware» more  ASYNC 2003»
15 years 11 months ago
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
Thomas Villiger, Hubert Kaeslin, Frank K. Gür...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 11 months ago
Area Fill Generation With Inherent Data Volume Reduction
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
15 years 11 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
GLVLSI
2003
IEEE
153views VLSI» more  GLVLSI 2003»
15 years 11 months ago
FORCE: a fast and easy-to-implement variable-ordering heuristic
The MINCE heuristic for variable-ordering [1] successfully reduces the size of BDDs and can accelerate SAT-solving. Applications to reachability analysis have also been successful...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 11 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...