2449 search results - page 239 / 490 » VLSI |
163
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
147
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we present a clustering based algorithm for acyclic multi-way partitioning. Many existing partitioning algorithms have shown that clustering can effectively improv...
151
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
137
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ISVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
151
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SLIP
2003
ACM
15 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...