2449 search results - page 249 / 490 » VLSI |
145
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FCCM
1999
IEEE
15 years 10 months ago
1999
IEEE
We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rat...
130
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GLVLSI
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
136
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ICPP
1999
IEEE
15 years 10 months ago
1999
IEEE
A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-...
154
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VLSID
1999
IEEE
15 years 10 months ago
1999
IEEE
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
170
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VLSID
1999
IEEE
15 years 10 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...