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ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
15 years 10 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
15 years 10 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
FCCM
1997
IEEE
118views VLSI» more  FCCM 1997»
15 years 10 months ago
Computing kernels implemented with a wormhole RTR CCM
The Wormhole Run-Time Reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data pow...
Ray Bittner, Peter M. Athanas
FCCM
1997
IEEE
111views VLSI» more  FCCM 1997»
15 years 10 months ago
Real-time stereo vision on the PARTS reconfigurable computer
This paper describes a powerful, scalable, reconfigurable computer called the PARTS engine. The PARTS engine consists of 16 Xilinx 4025 FPGAs, and 16 one-megabyte SRAMs. The FPGAs...
John Woodfill, Brian Von Herzen
VLSID
1997
IEEE
399views VLSI» more  VLSID 1997»
15 years 10 months ago
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
Pradip Mandal, V. Visvanathan