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VLSID
2002
IEEE
79views VLSI» more  VLSID 2002»
16 years 6 months ago
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, ...
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VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
16 years 6 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu
VLSID
2002
IEEE
111views VLSI» more  VLSID 2002»
16 years 6 months ago
Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design
This paper presents the applicability of a cosimulation methodology based on an object-oriented simulation environment, to multi-domain and multi-language systems design. This met...
Ahmed Amine Jerraya, Benoît Charlot, Gabriel...
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
16 years 6 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
16 years 6 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P...