Sciweavers

2449 search results - page 273 / 490
» VLSI
Sort
View
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
16 years 16 days ago
Testing Flash Memories for Tunnel Oxide Defects
— Testing non volatile memories for tunnel oxide defects is one of the most important aspects to guarantee cell reliability. Defective tunnel oxide layer in core memory cells can...
Mohammad Gh. Mohammad, Kewal K. Saluja
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
16 years 15 days ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
DFT
2007
IEEE
109views VLSI» more  DFT 2007»
16 years 15 days ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...
FCCM
2007
IEEE
154views VLSI» more  FCCM 2007»
16 years 15 days ago
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems
This paper presents a code compression and on-thefly decompression scheme suitable for coarse-grain reconfigurable technologies. A novel unit-grouping dictionary based compression...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
FCCM
2007
IEEE
101views VLSI» more  FCCM 2007»
16 years 15 days ago
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...