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FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
15 years 11 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
135
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FCCM
2005
IEEE
142views VLSI» more  FCCM 2005»
15 years 11 months ago
FPGA-Based Vector Processing for Solving Sparse Sets of Equations
The solution to a set of sparse linear equations Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vect...
Muhammad Z. Hasan, Sotirios G. Ziavras
126
Voted
FCCM
2005
IEEE
96views VLSI» more  FCCM 2005»
15 years 11 months ago
FPGA-Based CDMA Switch for Networks-on-Chip
This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networkson-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device u...
Daewook Kim, Manho Kim, Gerald E. Sobelman
FCCM
2005
IEEE
106views VLSI» more  FCCM 2005»
15 years 11 months ago
High-Performance FPGA-Based General Reduction Methods
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability t...
Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
15 years 11 months ago
Low power repeaters driving RLC interconnects with delay and bandwidth constraints
— Interconnect plays an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power,...
Guoqing Chen, Eby G. Friedman