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ISCAS
2005
IEEE
114views Hardware» more  ISCAS 2005»
15 years 11 months ago
Performance analysis by topology indexed lookup tables
— Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, ...
P. Agarwal, A. Vidyarthi, Patrick H. Madden
ISVLSI
2005
IEEE
69views VLSI» more  ISVLSI 2005»
15 years 11 months ago
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, E...
ISVLSI
2005
IEEE
124views VLSI» more  ISVLSI 2005»
15 years 11 months ago
Boost Logic: A High Speed Energy Recovery Circuit Family
In this paper, we propose Boost Logic, a logic family which relies on voltage scaling, gate overdrive and energy recovery techniques to achieve high energy efficiency at frequenc...
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad ...
ISVLSI
2005
IEEE
97views VLSI» more  ISVLSI 2005»
15 years 11 months ago
A High Performance Hybrid Wave-Pipelined Multiplier
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-b...
Suryanarayana Tatapudi, José G. Delgado-Fri...
VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
15 years 11 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury