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ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
15 years 10 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
ISLPED
1999
ACM
129views Hardware» more  ISLPED 1999»
15 years 10 months ago
Power scalable processing using distributed arithmetic
A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs c...
Rajeevan Amirtharajah, Thucydides Xanthopoulos, An...
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
15 years 10 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
ICIP
1999
IEEE
15 years 10 months ago
A New Anti-Aliasing Algorithm for Computer Graphics Images
This paper presents an area-filtering algorithm for antialiasing technique of computer graphics images. It can be applied to low-resolution image, which the aliasing effect is mor...
Yuan-Hau Yeh, Chen-Yi Lee
ISCAS
1999
IEEE
61views Hardware» more  ISCAS 1999»
15 years 10 months ago
A transformation for computational latency reduction in turbo-MAP decoding
The SOVA and the log-MAP are commonly used in turbo decoding. In this paper, we propose to modify the sliding window MAP-algorithm in [5]to reduce the computational delay even fur...
Arun Raghupathy, K. J. Ray Liu