Abstract--The rectilinear Steiner tree (RST) problem is of essential importance to the automatic interconnect optimization for VLSI design. In this paper, we present a class of pro...
In this article, we consider the estimation of exponential sums along the points of the reduction mod pm of a p-adic analytic submanifold of Zn p . More precisely, we extend Igusaâ...
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...