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JCO
2011
115views more  JCO 2011»
15 years 1 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
185
Voted
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
15 years 11 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
DAC
2007
ACM
16 years 7 months ago
Fast Min-Cost Buffer Insertion under Process Variations
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
Ruiming Chen, Hai Zhou
DAC
2003
ACM
16 years 7 months ago
Implications of technology scaling on leakage reduction techniques
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishn...
DAC
2004
ACM
16 years 7 months ago
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subprobl...
Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dy...