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VLSID
2008
IEEE
153views VLSI» more  VLSID 2008»
16 years 6 months ago
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
Yuanlin Lu, Vishwani D. Agrawal
VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
16 years 6 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
VLSID
2007
IEEE
91views VLSI» more  VLSID 2007»
16 years 6 months ago
Reusing Learned Information in SAT-based ATPG
The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on larg...
Görschwin Fey, Rolf Drechsler, Tim Warode
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 6 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
16 years 6 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan