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VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
16 years 6 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
16 years 6 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
VLSID
2007
IEEE
103views VLSI» more  VLSID 2007»
16 years 6 months ago
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Abstract-- This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variation...
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopala...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
16 years 6 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
VLSID
2006
IEEE
83views VLSI» more  VLSID 2006»
16 years 6 months ago
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics
In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching...
Amitava Bhaduri, Ranga Vemuri