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VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
16 years 5 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
16 years 5 months ago
Automatic Model Refinement for Fast Architecture Exploration
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...
Junyu Peng, Samar Abdi, Daniel Gajski
VLSID
2002
IEEE
83views VLSI» more  VLSID 2002»
16 years 5 months ago
Identifying Redundant Wire Replacements for Synthesis and Verification
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
Katarzyna Radecka, Zeljko Zilic
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
16 years 5 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
16 years 5 months ago
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...