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VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 5 months ago
Design of Asynchronous Controllers with Delay Insensitive Interface
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
Hiroshi Saito, Alex Kondratyev, Takashi Nanya
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 5 months ago
Register Transfer Operation Analysis during Data Path Verification
A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...
D. Sarkar
VLSID
2002
IEEE
174views VLSI» more  VLSID 2002»
16 years 5 months ago
Architecture Implementation Using the Machine Description Language LISA
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, ...
122
Voted
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
16 years 5 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
119
Voted
VLSID
2002
IEEE
60views VLSI» more  VLSID 2002»
16 years 5 months ago
Transistor Flaring in Deep Submicron-Design Considerations
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R....