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123
Voted
ICCD
2004
IEEE
16 years 2 months ago
2004
IEEE
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
129
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ICCD
2001
IEEE
16 years 1 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
123
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ICCAD
2006
IEEE
16 years 1 months ago
2006
IEEE
As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode insertion and jumper in...
124
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ICCAD
2006
IEEE
16 years 1 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
128
Voted
ICCAD
2003
IEEE
16 years 1 months ago
2003
IEEE
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation f...