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DFT
2009
IEEE
106views VLSI» more  DFT 2009»
15 years 11 months ago
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
FCCM
2009
IEEE
165views VLSI» more  FCCM 2009»
15 years 11 months ago
Accelerating Quadrature Methods for Option Valuation
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
Anson H. T. Tse, David B. Thomas, Wayne Luk
FCCM
2009
IEEE
133views VLSI» more  FCCM 2009»
15 years 11 months ago
Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks
—Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources....
Rafael Garcia, Ann Gordon-Ross, Alan D. George
FCCM
2009
IEEE
190views VLSI» more  FCCM 2009»
15 years 11 months ago
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
Brad L. Hutchings, Brent E. Nelson, Stephen West, ...
FCCM
2009
IEEE
192views VLSI» more  FCCM 2009»
15 years 11 months ago
FPGA Floating Point Datapath Compiler
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
Martin Langhammer, Tom VanCourt