Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
—Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources....
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
Brad L. Hutchings, Brent E. Nelson, Stephen West, ...
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...