The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore ar...
Abstract: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Implementing long-range forces, however, has only recently been address...
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
This paper introduces a parameterisable, application and platform-independent, hybrid memory sub-system for custom hardware. This memory sub-system consists of a scratchpad memory...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...