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ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
15 years 11 months ago
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of ion. A possible sol...
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide P...
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
15 years 11 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
15 years 11 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 11 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
15 years 11 months ago
Embedded Support Vector Machine : Architectural Enhancements and Evaluation
In recent years, research and development in the field of machine learning and classification techniques have gained paramount importance. The future generation of intelligent e...
Soumyajit Dey, Monu Kedia, Niket Agarwal, Anupam B...