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FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
15 years 11 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
15 years 11 months ago
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
Brad Matthews, Itamar Elhanany
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
15 years 11 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
ICMCS
2006
IEEE
140views Multimedia» more  ICMCS 2006»
15 years 11 months ago
A 3D Spatio-Temporal Motion Estimation Algorithm for Video Coding
This paper presents a new spatio-temporal motion estimation algorithm for video coding. The algorithm is based on optimization theory and consists of the strategies including 3D s...
Gwo Giun Lee, Ming-Jiun Wang, He-Yuan Lin, Drew We...
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ICMCS
2006
IEEE
137views Multimedia» more  ICMCS 2006»
15 years 11 months ago
An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder
This paper proposes an efficient reference frame storage scheme for HDTV VLSI decoder to reduce external memory bandwidth requirement. The proposed scheme consists of the pixel du...
Peng Zhang, Wen Gao, Di Wu, Don Xie