2449 search results - page 324 / 490 » VLSI |
111
Voted
IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper,...
127
Voted
IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
141
Voted
IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
The hierarchical hypercube network is suitable for massively parallel systems. An appealing property of this network is the low number of connections per processor, which can faci...
113
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ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
153
click to vote
ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...