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112
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ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
15 years 11 months ago
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures ...
Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsi...
ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
15 years 11 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
VLSID
2006
IEEE
71views VLSI» more  VLSID 2006»
15 years 11 months ago
Clockless Pipelining for Coarse Grain Datapaths
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Abdelhalim Alsharqawi, Abdel Ejnioui
120
Voted
VLSID
2006
IEEE
87views VLSI» more  VLSID 2006»
15 years 11 months ago
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B...
VLSID
2006
IEEE
143views VLSI» more  VLSID 2006»
15 years 11 months ago
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar