Sciweavers

2449 search results - page 330 / 490
» VLSI
Sort
View
FCCM
2005
IEEE
107views VLSI» more  FCCM 2005»
15 years 10 months ago
Hardware Solution to Java Compressed Heap
Java technology has been integrated into mobile/wireless computing because of its rich support to portability (crossplatform nature), reusability (development libraries), and shor...
Mayumi Kato, Chia-Tien Dan Lo
FCCM
2005
IEEE
93views VLSI» more  FCCM 2005»
15 years 10 months ago
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
Zion Kwok, Steven J. E. Wilton
FCCM
2005
IEEE
84views VLSI» more  FCCM 2005»
15 years 10 months ago
Prototyping Architectural Support for Program Rollback Using FPGAs
This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compile...
Radu Teodorescu, Josep Torrellas
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 10 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
15 years 10 months ago
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
Dongku Kang, Yiran Chen, Kaushik Roy