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PATMOS
2005
Springer
15 years 10 months ago
Efficient Simulation of Power/Ground Networks with Package and Vias
As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Ta...
SAMOS
2005
Springer
15 years 10 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
DAC
2004
ACM
15 years 10 months ago
Low voltage swing logic circuits for a Pentium 4 processor integer core
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
Daniel J. Deleganes, Micah Barany, George Geannopo...
126
Voted
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
15 years 10 months ago
Multilevel routing with antenna avoidance
As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide...
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
126
Voted
ISPD
2004
ACM
92views Hardware» more  ISPD 2004»
15 years 10 months ago
A predictive distributed congestion metric and its application to technology mapping
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant S...