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DFT
2003
IEEE
79views VLSI» more  DFT 2003»
15 years 10 months ago
Hybrid BIST Using an Incrementally Guided LFSR
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
C. V. Krishna, Nur A. Touba
141
Voted
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
15 years 10 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
15 years 10 months ago
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
Kartik Mohanram, Nur A. Touba
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
15 years 10 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
170
Voted
DFT
2003
IEEE
246views VLSI» more  DFT 2003»
15 years 10 months ago
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...
Konstantinos Rokas, Yiorgos Makris, Dimitris Gizop...