2449 search results - page 340 / 490 » VLSI |
109
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ITC
2002
IEEE
15 years 10 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
142
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VTS
2002
IEEE
15 years 9 months ago
2002
IEEE
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverages. The very important class of dynamic fault, therefore cannot be ignored an...
149
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VTS
2002
IEEE
15 years 9 months ago
2002
IEEE
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
144
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VTS
2002
IEEE
15 years 9 months ago
2002
IEEE
Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is diffic...
146
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VTS
2002
IEEE
15 years 9 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...