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IPPS
1999
IEEE
15 years 9 months ago
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer
This paper describes a dynamically reconfigurable hardware-based computer called the Plastic Cell Architecture (PCA). PCA consists of dualstructured sea-of -cells that consist of a...
Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Mino...
136
Voted
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
15 years 9 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
EVOW
1999
Springer
15 years 9 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
136
Voted
DATE
1998
IEEE
141views Hardware» more  DATE 1998»
15 years 9 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...
DATE
1998
IEEE
76views Hardware» more  DATE 1998»
15 years 9 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram