Sciweavers

2449 search results - page 359 / 490
» VLSI
Sort
View
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
15 years 10 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
GLVLSI
2006
IEEE
119views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Thermal analysis of a 3D die-stacked high-performance microprocessor
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
Kiran Puttaswamy, Gabriel H. Loh
142
Voted
ISCAS
2006
IEEE
118views Hardware» more  ISCAS 2006»
15 years 10 months ago
A robust continuous-time multi-dithering technique for laser communications using adaptive optics
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
15 years 10 months ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 10 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt