2449 search results - page 370 / 490 » VLSI |
191
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FCCM
2011
IEEE
14 years 8 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
190
Voted
FCCM
2011
IEEE
14 years 8 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
274
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GLVLSI
2011
IEEE
14 years 8 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
154
Voted
ISCAS
2011
IEEE
14 years 8 months ago
2011
IEEE
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...
203
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ISPD
2012
ACM
14 years 3 days ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...