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VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
16 years 4 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
16 years 4 months ago
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 4 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
16 years 4 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
VLSID
2005
IEEE
126views VLSI» more  VLSID 2005»
16 years 4 months ago
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
Jaijeet S. Roychowdhury