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VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
16 years 4 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
16 years 4 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
16 years 4 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
VLSID
2003
IEEE
110views VLSI» more  VLSID 2003»
16 years 4 months ago
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems
Control dominated embedded systems have to be designed for fast reaction to asynchronous external events occurring in the environment. Such systems must be able to perform signal ...
Partha S. Roop, Zoran A. Salcic, Morteza Biglari-A...
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
16 years 4 months ago
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
Sanjukta Bhanja, N. Ranganathan