As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus...
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstr...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...