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ICCD
2007
IEEE
111views Hardware» more  ICCD 2007»
16 years 1 months ago
On modeling impact of sub-wavelength lithography on transistors
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Aswin Sreedhar, Sandip Kundu
ICCD
2005
IEEE
111views Hardware» more  ICCD 2005»
16 years 1 months ago
Supply Voltage Degradation Aware Analytical Placement
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus...
Andrew B. Kahng, Bao Liu, Qinke Wang
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
16 years 1 months ago
Precomputation-based Guarding for Dynamic and Leakage Power Reduction
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, I...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 1 months ago
Design Flow Enhancements for DNA Arrays
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstr...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
ICCD
2002
IEEE
160views Hardware» more  ICCD 2002»
16 years 1 months ago
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...
Sanjukta Bhanja, N. Ranganathan