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ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
15 years 11 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
DAC
2009
ACM
15 years 11 months ago
Information hiding for trusted system design
For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verifica...
Junjun Gu, Gang Qu, Qiang Zhou
CP
2009
Springer
15 years 11 months ago
Pin Assignment Using Stochastic Local Search Constraint Programming
Abstract. VLSI chips design is becoming increasingly complex and calling for more and more automation. Many chip design problems can be formulated naturally as constraint problems ...
Bella Dubrov, Haggai Eran, Ari Freund, Edward F. M...
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
15 years 11 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
DFT
2009
IEEE
155views VLSI» more  DFT 2009»
15 years 11 months ago
Errors in DNA Self-Assembly by Synthesized Tile Sets
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabri...